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Variable latency L1 data cache architecture design in multi-core processor under process variation

Joonho Kong 2015년

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논문상세정보

- 저자 Joonho Kong
- 제어번호 101701332
- 학술지명 韓國컴퓨터情報學會論文誌
- 권호사항 Vol. 20 No. 9 [ 2015 ]
- 발행처 한국컴퓨터정보학회
- 발행처 URL http://www.ksci.re.kr
- 자료유형 학술저널
- 수록면 1-10 ( 10쪽)
- 언어 Korean
- 출판년도 2015
- 등재정보 KCI등재
- 판매처 누리미디어
- 주제어 Cacheaccesstimefailure Multi-core architecture process variation Processor yield loss Variable latency cache architecture
- 참고문헌( 22)
유사주제 논문( 8)
- process variation 8건

인용/피인용

Variable latency L1 data cache architecture desig ...

' Variable latency L1 data cache architecture design in multi-core processor under process variation' 의 주제별 논문영향력

논문영향력 요약
동일주제 총논문수	논문피인용 총횟수	주제별 논문영향력의 평균
주제	cacheaccesstimefailure multi-core architecture process variation processor yield loss variable latency cache architecture
13	0	0.0%

논문영향력
주제		주제별 논문수	주제별 논문영향력
주제어	cacheaccesstimefailure	1	0.0%
	multi-core architecture	1	0.0%
	process variation	9	0.0%
	processor yield loss	1	0.0%
	variable latency cache archit ...	1	0.0%
계		13	0.0%
* 다른 주제어 보유 논문에서 피인용된 횟수

' Variable latency L1 data cache architecture design in multi-core processor under process variation' 의 참고문헌

임베디드 시스템에서 후방 분기 명령어 정보를 이용한 저전력 명령어 캐쉬 설계 기법
양나라 한국컴퓨터정보학회논문지 13 (6) : 33 ~ 40 [2008]
멀티 코어 프로세서를 위한 저전력 필터 캐쉬 설계 기법
박영진 한국컴퓨터정보학회논문지 14 (12) : 9 ~ 16 [2009]
Yield-Aware Cache Architectures
S. Ozdemir Proc. of IEEE/ACM Int’l Symposium on Microarchitecture : 15 ~ 25 [2006]
Working with process variation aware caches
Mutyam, M. Narayanan, V. Proc. of Design, Automation and Test in Europe : 1152 ~ 1157 [2007]
Variation-tolerant circuits: circuit solutions and techniques
Bowman, K. De, V. Tschanz, J. Proc. of Design Automation Conference : 762 ~ 763 [2005]
Variable latency caches for nanoscale processor
S. Ozdemir Proc. of 2007 ACM/IEEE Conference on Supercomputing : 1 ~ 10 [2007]
Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation
T. Carlson Proc. of the 2011 International Conference for High Performance Computing, Networking, Storage and Analysis (SC) : 1 ~ 12 [2011]
Selective wordline voltage boosting for caches to manage yield under process variations
Chung, S.W. Kong, J. Memik, G. Ozdemir, S. Pan, Y. Proc. of Design Automation Conference : 57 ~ 62 [2009]
SAVS: a self-adaptive variable supply-voltage technique for process-tolerant and power-efficient multi-issue superscalar processor design
H. Li Proc. of Asia South Pacific Design Automation Conference [2006]
Quantifying and coping with parametric variations in 3D-stacked microarchitectures
Choudhary, A. Das, A. Loh, G. Memik, G. Ozdemir, S. Pan, Y. Proc. of Design Automation Conference : 144 ~ 149 [2010]
Process variation in embedded memories: failure analysis and variation aware architecture
A. Agarwal IEEE Jnl. of Solid-State Circuits 40 (9) [2005]
Process Variation-Aware Adaptive Cache Architecture and Management
M. Mutyam IEEE Trans. Computers 58 (7) : 865 ~ 877 [2009]
Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well Adaptive Body Biasing (IWABB)
J. Gregg Proc. of IEEE Int’l Symposium on Quality Electronic Design [2007]
Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing
R. Teodorescu Proc. of IEEE/ACM Int’l Symposium on Microarchitecture : 27 ~ 42 [2007]
McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures
S. Li Proc. of 42nd Annual IEEE/ACM International Symposium on Microarchitecture : 469 ~ 480 [2009]
Intel® Atom™ Processor C2750 (4M Cache, 2.40 GHz)
Fine-Grain Voltage Tuned Cache Architecture for Yield Management Under Process Variations
J. Kong IEEE Trans. VLSI Syst 20 (8) : 1532 ~ 1536 [2012]
Exploiting narrow-width values for process variation-tolerant 3-D microprocessors
Chung, S.W. Kong, J. Proc. of Design Automation Conference : 1197 ~ 1206 [2012]
Computer Organization and Design The Hardware/Software Interface (ser. Comput. Architecture and Design), 4th edition
D. A. Patterson Morgan Kaufmann [2012]
An energy-efficient last-level cache architecture for process variation-tolerant 3D microprocessors
J. Kong IEEE Trans. Computers, published online
A process-tolerant cache architecture for improved yield in nanoscale technologies
A. Agarwal IEEE Transaction on VLSI Systems 13 (1) : 27 ~ 38 [2005]
4Ghz 고성능 CPU 위한 캐시 메모리 시스템
정보성 한국컴퓨터정보학회논문지 18 (2) : 1 ~ 8 [2013]

Variable latency L1 data cache architecture design in multi-core processor under process variation

유사주제 논문( 8)

' Variable latency L1 data cache architecture design in multi-core processor under process variation' 의 주제별 논문영향력

주제별 논문영향력

' Variable latency L1 data cache architecture design in multi-core processor under process variation' 의 참고문헌

' Variable latency L1 data cache architecture design in multi-core processor under process variation' 의 유사주제( ) 논문