연구동향 분석

An Adaptive-Bandwidth Referenceless CDR with Small-area Coarse and Fine Frequency Detectors

Hye-Jung Kwon Ji-Hoon Lim Byungsub Kim Jae-Yoon Sim Hong-June Park 2015년

논문상세정보
인용/피인용
' An Adaptive-Bandwidth Referenceless CDR with Small-area Coarse and Fine Frequency Detectors' 의 주제별 논문영향력
논문영향력 선정 방법
논문영향력 요약
주제
  • 전자공학
  • adaptive bandwidth
  • clockanddatarecoverycircuit
  • finefrequencydetection
  • jittertolerance
  • referenceless
동일주제 총논문수 논문피인용 총횟수 주제별 논문영향력의 평균
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' An Adaptive-Bandwidth Referenceless CDR with Small-area Coarse and Fine Frequency Detectors' 의 참고문헌

  • Monolithic Phase-Locked Loops and Clock Recovery Circuits:Theory and Design : 107 ~ 114
    Razavi. B [1996]
  • Full-Rate Bang-Bang Phase/Frequency Detectors for Unilateral Continuous-Rate CDRs
    Shao-Hung Lin IEEE Transactions on Circuits ans Systems—II: Express briefs 55 (12) [2008]
  • Frequency Detectors for PLL Acquisition in Timing and Carrier R.ecovery
    David G. Messerschmitt IEEE Transactions on Communications COM-27 (9) [1979]
  • Digital Clock and Data Recovery Circuit Design: Challenges and Tradeoffs
    Mrunmay Talegaonkar Custom Integrated Circuits Conference (CICC), 2011 IEEE : 1 ~ 8 [2011]
  • Analysis of a Frequency Acquisition Technique With a Stochastic Reference Clock Generator
    Jinho Han IEEE Transactions on Circuits ans Systems—II: Express briefs 59 (6) : 336 ~ 340 [2012]
  • An 8.5–11.5-Gbps SONET Transceiver With Referenceless Frequency Acquisition
    Namik Kocaman IEEE J. Solid-State Circuits 48 (8) : 1875 ~ 1884 [2013]
  • A Wide-Tracking Range Clock and Data Recovery Circuit
    Pavan Kumar Hanumolu IEEE J. Solid-State Circuits 43 (2) : 268 ~ 278 [2008]
  • A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy
    Hyung-Joon Jeon IEEE J. Solid-State Circuits 48 (6) [2013]
  • A 650Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rate
    S.-K. Lee IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers : 184 ~ 185 [2009]
  • A 4-to-10.5Gb/s 2.2mW/Gb/s Continuous-Rate Digital CDR with Automatic Frequency Acquisition in 65nm CMOS
    Guanghua Shu IEEE ISSCC Dig. Tech. Papers : 150 ~ 152 [2014]
  • A 3.125- Gb/s Clock and Data Recovery Circuit for the 10- Gbase-LX4 Ethernet
    R.-J. Yang IEEE J. Solid-State Circuits 39 (8) : 1356 ~ 1360 [2004]
  • A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition
    Jri Lee IEEE J. Solid- State Circuits 44 (12) : 3590 ~ 3602 [2009]
  • A 1–16-Gb/s Wide-Range Clock/Data Recovery Circuit With a Bidirectional Frequency Detector
    Chang-Lin Hsieh IEEE Transactions on Circuits ans Systems—II: Express briefs 58 (8) [2011]
  • A 180-Mb/s to 3.2-Gb/s, continuousrate, fast-locking CDR without using external reference clock
    M.-S. Hwang Proc. IEEE Asian Solid-State Circuits Conf : 144 ~ 147 [2007]
  • A 155. 52 Mbps–3. 125 Gbps Continuous-Rate Clock and Data Recovery Circuit
    Rong-Jyi Yang IEEE J. Solid-State Circuits 41 (6) : 1380 ~ 1390 [2006]
  • A 12.5- Mb/s to 2.7-Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate read back
    D. Dalton Solid-State Circuits, IEEE J 40 (12) : 2713 ~ 2725 [2005]
  • A 10 to 11.5GHz Rotational Phase and Frequency Detector for Clock Recovery Circuit
    Fan-Ta Chen Circuits and Systems (ISCAS), 2011 IEEE International Symposium on : 185 ~ 188 [2011]
  • A 1.62 Gb/s–2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection
    Junyoung Song IEEE Trans. on Ciruits and System I: Regular papers 60 (2) : 268 ~ 278 [2013]
  • A 1.2–6 Gb/s, 4.2 pJ/Bit Clock & Data Recovery Circuit With High Jitter Tolerance in 0.14 m CMOS
    Arnoud P. van der Wel IEEE J. Solid-State Circuits 47 (7) : 1768 ~ 1775 [2012]
  • A 1.0–4.0- Gb/s All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control
    Heesoo Song IEEE J. Solid-State Circuits 46 (2) [2011]
  • A 0.5-to- 2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance
    Rajesh Inti IEEE J. Solid-State Circuits 46 (12) : 3150 ~ 3162 [2011]
  • A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration
    Amr Elshazly IEEE J. Solid-State Circuits 46 (12) [2011]
  • 1 Gb/s gatedoscillator burst mode CDR for half-rate clock recovery
    Pyung-Su Han IEEE J. Semiconductor Technology and Science 4 (4) [2004]
  • 0.6–2.7-Gb/s Referenceless Parallel CDR With a Stochastic Dispersion-Tolerant Frequency Acquisition Technique
    Jinho Han IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (6) [2014]