연구동향 분석

An Adaptive Equalizer for High-Speed Receiver using a CDR-Assisted All-Digital Jitter Measurement

Jong-Hoon Kim Ji-Hoon Lim Byungsub Kim Jae-Yoon Sim Hong-June Park 2015년

논문상세정보
인용/피인용
' An Adaptive Equalizer for High-Speed Receiver using a CDR-Assisted All-Digital Jitter Measurement' 의 주제별 논문영향력
논문영향력 선정 방법
논문영향력 요약
주제
  • 전자공학
  • adaptive equalizer
  • jittermeasurement
  • usb 3.0 high-speed receiver
동일주제 총논문수 논문피인용 총횟수 주제별 논문영향력의 평균
2,300 0

0.0%

' An Adaptive Equalizer for High-Speed Receiver using a CDR-Assisted All-Digital Jitter Measurement' 의 참고문헌

  • The Design of Continuous-Time Linear Equalizers Using Model Order Reduction Techniques
    W.-T.Beyene IEEE-EPEP : 187 ~ 190 [2008]
  • Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BERBased Metric
    E-Hung Chen IEEE J. Solid-State Circuits 43 (9) : 2144 ~ 2156 [2008]
  • Equalization and clock and data recovery techniques for 10-Gb/s CMOS serial-link receivers
    S. Gondi IEEE J. Solid-State Circuits 42 (9) : 1999 ~ 2011 [2007]
  • An 8-Gb/s Inductorless Adaptive Passive Equalizer in 0.18- μm CMOS Technology
    J.-W.Moon J. Semicond. Technol. ci 12 (4) : 405 ~ 410 [2012]
  • A multigigabit backplane transceiver core in 0.13-um CMOS with a powerefficient equalization architecture
    K. Krishna IEEE J. Solid- State Circuits 40 (12) : 2658 ~ 2666 [2005]
  • A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface
    H.-J. Chi IEEE J.Solid-State Circuits 46 (9) : 897 ~ 910 [2011]
  • A 6Gb/s RX Equalizer Adapted Using Direct Measurement of the Equalizer Output Amplitude
    H. Uchiki ISSCC Dig. Tech. Papers : 104 ~ 106 [2008]
  • A 6.4 Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization
    T. Beukema IEEE J. Solid-State Circuits : 2633 ~ 2645 [2005]
  • A 6.25-Gb/s Binary Transceiver in 0.13-μm CMOS for Serial Data Transmission Across High Loss Legacy Backplane Channels
    R. Payne IEEE J. Solid-State Circuits 40 : 2646 ~ 2657 [2005]
  • A 5.4Gb/s Adaptive Equalizer Using Asynchronous-Sampling Histograms
    W.S. Kim ISSCC Dig. Tech. Papers : 358 ~ 359 [2011]
  • A 40 Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery
    C.-F. Liao IEEE J. Solid-State Circuits 43 (11) : 2492 ~ 2502 [2008]
  • A 4.8–6.4-Gb/s serial link for backplane applications using decision feedback equalization
    V. Balan IEEE J.Solid-State Circuits 40 (9) : 1957 ~ 1967 [2005]
  • A 20-Gbps adaptive equalizer in 0.13-μm CMOS technology
    J. Lee IEEE J. Solid-State Circuits 41 (9) : 2058 ~ 2066 [2006]
  • A 10Gb/s CMOS Adaptive Equalizer for Backplane Applications
    S. Gondi ISSCC Dig. Tech. Papers : 328 ~ 329 [2005]
  • A 10-Gb/s two-dimensional eyeopening monitor in 0.13-μm standard CMOS
    B. Analui IEEE J. Solid-State Circuits 40 (12) : 2689 ~ 2699 [2005]
  • A 10-Gb/s CMOS serial-link receiver using eye-opening monitoring for adaptive equalization and for clock and data recovery
    T. Suttorp IEEE Custom Integrated Circuits Conf : 277 ~ 280 [2007]
  • A 10 Gb/s eye-opening monitor in 0.13 um CMOS
    B. Analui IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers : 332 ~ 333 [2005]
  • A 10 Gb/s 5- Tap-DFE/4-Tap-FFE transceiver in 90 nm CMOS
    M. Meghelli IEEE Int.Solid-State Circuits Conf. Dig. Tech. Papers : 80 ~ 81 [2006]
  • A 0.18 _m CMOS 3.5-Gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method
    J.-S. Choi IEEE J. Solid-State Circuits : 419 ~ 425 [2004]
  • 5-Gb/s 0.25-μm CMOS jittertolerant variable-interval oversampling clock data recovery circuit
    M.-S. Hwang IEEE J. Solid-State Circuits 37 (12) : 1822 ~ 1830 [2002]