연구동향 분석

공정 코너별 LVCC 마진 특성을 이용한 전력 소모 개선 Voltage Binning 기법

이원준(Won Jun Lee) 한태희(Tae Hee Han) 2014년

논문상세정보
인용/피인용
' 공정 코너별 LVCC 마진 특성을 이용한 전력 소모 개선 Voltage Binning 기법' 의 주제별 논문영향력
논문영향력 선정 방법
논문영향력 요약
주제
  • 전자공학
  • postsilicon
  • power saving
  • process variation
  • processcorner
  • voltagebinning
동일주제 총논문수 논문피인용 총횟수 주제별 논문영향력의 평균
2,322 0

0.0%

' 공정 코너별 LVCC 마진 특성을 이용한 전력 소모 개선 Voltage Binning 기법' 의 참고문헌

  • Voltage Binning Under Process Variation
    V. Zolotov IEEE/ACM Int. Conf. on Computer-Aided Design Digest of Tech. Paper (ICCAD) : 425 ~ 432 [2009]
  • Using Selective Voltage Binning to Maximize Yield
    S. Lichtensteiger Advanced Semiconductor Manufacturing Conference (ASMC) : 7 ~ 10 [2012]
  • Optimal Body Bias Selection for Leakage Improvement and Process Compensation over Different Technology Generations
    C. Neau Int. Symposium on Low Power Electronics and Design (ISLPED) : 116 ~ 121 [2003]
  • Integrated Circuit Design Closure Method for Selective Voltage Binning
    M. W. Kuemerle U. S. Patent 7475366 [2009]
  • Effectiveness of Adaptive Supply Voltage and Body Bias for Reducing Impact of Parameter Variations in Low Power and High Performance Microprocessors
    J. W. Tschanz IEEE Journal of Solid State Circuits 38 (5) : 826 ~ 829 [2003]
  • Comparison of Adaptive Body Bias and Adaptive Supply Voltage for Improving Delay and Leakage under the Presence of Process Variation
    T. Chen IEEE Transaction on very large scale integration systems 11 (5) : 888 ~ 899 [2003]
  • Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage
    J. W. Tschanz IEEE Journal of Solid State Circuits 37 (11) : 1396 ~ 1402 [2002]
  • A New Voltage Binning Technique for Yield Improvement Based on Graph Theory
    R. Shen Int. Symposium on Quality Electronic Design (ISQED) [2012]