'
A High-Speed Link Transmitter for Emulating Channel Attenuation with Logarithmic and Exponential Function = 대수함수와 지수함수를 통한 전송신로 손실을 모사한 고속신호 전송회로' 의 주제별 논문영향력
논문영향력 요약
주제
응용 물리
동일주제 총논문수
논문피인용 총횟수
주제별 논문영향력의 평균
4,649
0
0.0%
주제별 논문영향력
논문영향력
주제
주제별 논문수
주제별 피인용횟수
주제별 논문영향력
주제분류(KDC/DDC)
응용 물리
4,649
0
0.0%
계
4,649
0
0.0%
* 다른 주제어 보유 논문에서 피인용된 횟수
0
'
A High-Speed Link Transmitter for Emulating Channel Attenuation with Logarithmic and Exponential Function = 대수함수와 지수함수를 통한 전송신로 손실을 모사한 고속신호 전송회로' 의 참고문헌
Y. Choi, Y. Lee, S.-H. Baek, S.-J. Lee, and J. Kim, “A Field- Programmable Mixed-Signal IC with Time-Domain Configurable Analog Blocks,” in IEEE Symposium on VLSI Circuits, pp. 138-139, Jun. 2016.
William L. Barber, et.al., “A true logarithmic amplifier for radar IF applications,” IEEE J. Solid-State Circuits, vol. 15, no. 15, pp. 291-295, Jun. 1980.
W.Y. Shin, et al., “A 4.8Gb/s Impedance-Matched Bidirectional Multi- Drop Transceiver for High-Capacity Memory Interface,” in IEEE ISSCC Dig. Tech. Papers, pp.494-495, Feb. 2011.
W. Dally and J. Poulton., Digital Systems Engineering, New York: Cambridge University Press, 1998.
T. R. Arabi, et al., “On the Modeling of Conductor and Substrate Losses in Multiconductor, Multidielectric Transmission Line Systems,” IEEE Trans. Microw. Theory Tech., Vol. 39, No.7, pp.1090-1097, Jul. 1991.
Srikanth Gondi, and B. Razavi, “Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers,” in IEEE J. Solid-State Circuits, Vol.42, no. 9, pp. 1999-20111, Aug. 2007.
Sigang Ryu, et al., “Cell-Based Construction of Mixed-Signal Systems Using Co-Design Flow of IC Compiler and Custom Designer: A Digital LL Example,” in Proc. Synopsys SNUG, May. 2014.
S. Ryu, et al., “A 9.2-GHz Digital Phase-Locked Loop with Peaking-Free Transfer Function,” in IEEE J. Solid-State Circuits, Vol.49, no. 8, pp. 1773-1784, Aug. 2014.
S. Parikh, et al., “A 32Gb/s Wireline Receiver with a Low-Frequency Equalizer, CTLE and 2-Tap DFE in 28nm CMOS” in IEEE ISSCC Dig. Tech. Papers, pp.28-29, Feb. 2013.
R.-J. Yang and S.-I. Liu, “A 40–550 MHz Harmonic-Free All- Digital Delay- Locked Loop Using a Variable SAR Algorithm,” IEEE J. of Solid- State Circuits, Vol.42, no. 2, pp. 361–373, Feb. 2007.
R. Fukuda, et al., “Burst Cycle Data Compression Schemes for Pre-Fuse Wafer-Level Test in Large Scale High-Speed embedded DRAM,” in Symposium. VLSI Circuits Dig., pp.30-33, Jun. 2004.
M. L. Bushnell and V. D. Agrawal, Frontiers in Electronic Testing, vol. 17, Boston, MA: Kluwer Academic Publishers, 2002.
M. Horowitz, et al., “Fortifying Analog Models with Equivalence Checking and Coverage Analysis,” in Proc. ACM/IEEE Design Automation Conf. (DAC), pp. 425-430, Jun. 2010.
M. Burns, et al., An introduction to mixed-signal IC test and measurement, New York, NY: Oxford University Press, 2011.
Kyunghoon Kim, et al., "A 1.3-mW, 1.6-GHz Digital Delay-Locked Loop with Two-Cycle Locking Time and Dither-Free Tracking," in IEEE Symposium on VLSI Circuits, pp.158-159, Jun. 2013.
Kyu-Dong Hwang, et al., “A 16Gb/s/pin 8Gb GDDR6 DRAM with Bandwidth Extension Techniques for High-Speed Applications,” in IEEE ISSCC Dig. Tech. Papers, pp.210-211, Feb. 2018
Jeong-Kyoum Kim, et al., “A Fully Integrated 0.13-um CMOS 40-Gb/s Serial Link Transceiver,” IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1510-1521, May 2009.
Jaeha Kim. ECE4541. Class Lecture, Topic: “Link Noise Interference,” Dept. of Electrical and Computer Engineering, Seoul National University, Seoul, Mar. 2011.
Jaeha Kim, et al., “A 20-GHz Phase Locked Loop for ‐ 40Gb/s Serializing Transmitter in 0.13-um CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 899-908, Mar. 2006.
J. Lee, et al., “A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with Peripheral- base-Die Architecture and Small-Swing Technique on Heavy Load Interface,” in IEEE ISSCC Dig. Tech. Papers, pp.318-319, Feb. 2016.
J. H. Cho, et al., “A 1.2V 64Gb 341GB/S HBM2 stacked DRAM with spiral point-to-point TSV structure and improved bank group data control,” in IEEE ISSCC Dig. Tech. Papers, pp.208-209, Feb. 2018.
J. -R. Schrader, et al., “Pulse-Width Modulation Pre-Emphasis Applied in a Wireline Transmitter, Achieving 33 dB Loss Compensation at 5-Gb/s in 0.13-um CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 990-999, Mar. 2006.
H. K. Jung, et al., “A 4.35Gb/s/pin LPDDR4 I/O Interface with Multi- VOH Level Equalization Scheme and Duty Training Circuit for Mobile Applications,” in IEEE Symposium VLSI Circuits Dig., pp. 184-185, Jun. 2015.
H. Cirit, et al., “A 10Gb/s Half-UI IIR-Tap Transmitter in 40nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, pp.448-450, Feb. 2011.
G. E. Moore., “Cramming More Components onto Integrated Circuits,” Electronics, Apr. 1965.
Douglas, Signal Integrity Issues and Printed Circuit Board Design, Upper Saddle River, NJ: Prentice Hall, 2003, Chapter 10, pp 175-203
David McCallum, et al., “A migration path from 6.25 Gbps operation to 10 Gbps operation,” IEEE802.3ap, Portland, OR, Tech report, Jul. 2004.
David M. Pozar, Microwave Engineering, Edition 4.0, Hoboken, NJ: Wiley, 2011.
Chulwoo Kim, et al., “Memory Interfaces: Past, Present, and Future,” IEEE Solid-State Circuits Magazine, vol. 8, no.2, pp.23-34, Jun. 2016.
C.D. Holdenried, et al., “A DC–4-GHz true logarithmic amplifier: theory and implementation,” IEEE J. Solid-State Circuits, vol. 37, no. 10, pp. 1290-1299, Nov. 2002.
C. Svensson and C.H. Dermer, “Time Domain Modeling of Lossy Interconnects,” IEEE Trans. Advanced Packaging, Vol. 24, No.2, pp.191-196, May. 2001.
'
A High-Speed Link Transmitter for Emulating Channel Attenuation with Logarithmic and Exponential Function = 대수함수와 지수함수를 통한 전송신로 손실을 모사한 고속신호 전송회로'
의 유사주제(
) 논문