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Methodology for Solving Timing Closure Problem by Utilizing Adjustable Delay Clock Buffers

김주연 2018년
논문상세정보
' Methodology for Solving Timing Closure Problem by Utilizing Adjustable Delay Clock Buffers' 의 주제별 논문영향력
논문영향력 선정 방법
논문영향력 요약
주제
  • 응용 물리
  • adb
  • clock network design
  • clock skew
  • multiple power mode
동일주제 총논문수 논문피인용 총횟수 주제별 논문영향력의 평균
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0.0%

' Methodology for Solving Timing Closure Problem by Utilizing Adjustable Delay Clock Buffers' 의 참고문헌

  • “Nangate 45nm Open Cell Library.” http://www.nangate.com/
  • Y.-S. Su, W.-K. Hon, C.-C. Yang, S.-C. Chang, and Y.-J. Chang, “Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs,” in Proceedings of the 2009 IEEE/ACM International Conference on Computer Aided Design, Nov. 2009, pp. 535–538.
  • Y.-S. Su, W.-K. Hon, C.-C. Yang, S.-C. Chang, and Y.-J. Chang, “Clock skew minimization in multi-voltage mode designs using adjustable delay buffers,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 12, pp. 1921–1930, Dec. 2010.
  • X. Liu, M. C. Papaefthymiou, and E. G. Friedman, “Maximizing performance by retiming and clock skew scheduling,” in Proceedings of the 36th IEEE/ACM Design Automation Conference, Jun. 1999, pp. 231–236.
  • V. Nawale and T. W. Chen, “Optimal useful clock skew scheduling in the presence of variations using robust ilp formulations,” in Proceedings of the 2006 IEEE/ACM International Conference on Computer Aided Design, Nov. 2006, pp. 27–32.
  • V. Khandelwal and A. Srivastava, “Variability-driven formulation for simultaneous gate sizing and postsilicon tunability allocation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 4, pp. 610–620, Apr. 2008.
  • T.-Y. Kim and T. Kim, “Clock tree synthesis for tsv-based 3d ic designs,” ACM Transactions on Design Automation of Electronic Systems, vol. 16, no. 4, pp. 48:1–48:21, Oct. 2011.
  • T.-H. Chao, Y.-C. Hsu, J.-M. Ho, and A. B. Kahng, “Zero skew clock routing with minimum wirelength,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 39, no. 11, pp. 799– 814, Nov 1992.
  • T. Okamoto and J. Cong, “Buffered steiner tree construction with wire sizing for interconnect layout optimization,” in Proceedings of the 1996 IEEE/ACM International Conference on Computer Aided Design, Nov. 1996, pp. 44–49.
  • S. Tam, S. Rusu, U. Nagarji Desai, R. Kim, J. Zhang, and I. Young, “Clock generation and distribution for the first IA-64 microprocessor,” IEEE Journal of Solid- State Circuits, vol. 35, no. 11, pp. 1545–1552, Nov. 2000.
  • S. Hu and J. Hu, “Unified adaptivity optimization of clock and logic signals,” in Proceedings of 2007 IEEE/ACM International Conference on Computer-Aided Design, Nov. 2007, pp. 125–130.
  • R. S. Tsay, “Exact zero skew,” in 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers, Nov. 1991, pp. 336–339.
  • R. B. Deokar and S. S. Sapatnekar, “A graph-theoretic approach to clock skew optimization,” in Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, May 1994, pp. 407–410.
  • N. J. A. Kapoor and S. P. Khatri, “A novel clock distribution and dynamic deskewing methodology,” in Proceedings of the 2004 IEEE/ACM International Conference on Computer Aided Design, Nov. 2004, pp. 626–631.
  • M. Weiser, B. Welch, A. Demers, and S. Shenker, Scheduling for reduced CPU energy. Boston, MA: Springer US, 1996, pp. 449–471.
  • M. Edahiro, “A clustering-based optimization algorithm in zero-skew routings,” in Proceedings of the 30th IEEE/ACM Design Automation Conference, Jun. 1993, pp. 612–616.
  • K.Wang, Y. Ran, H. Jiang, and M. Marek-Sadowska, “General skew constrained clock network sizing based on sequential linear programming,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 5, pp. 773–782, May 2005.
  • K.-Y. Lin, H.-T. Lin, and T.-Y. Ho, “An efficient algorithm of adjustable delay buffer insertion for clock skew minimization in multiple dynamic supply voltage designs,” in Proceedings of the 2011 IEEE Asia and South Pacific Design Automation Conference, Jan. 2011, pp. 825–830.
  • K.-H. Lim, D. Joo, and T. Kim, “An optimal allocation algorithm of adjustable delay buffers and practical extensions for clock skew optimization in multiple power mode designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 3, pp. 392–405, Mar. 2013.
  • J.-L. Tsai, T.-H. Chen, and C.-P. Chen, “Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 4, pp. 565–572, Apr. 2004.
  • J.-L. Tsai, D. H. Baik, and C.-P. Chen, “A yield improvement methodology using pre- and post-silicon statistical clock scheduling,” in Proceedings of the 2004 IEEE/ACM International Conference on Computer Aided Design, Nov. 2004, pp. 611–618.
  • J.-L. Tsai and L. Zhang, “Statistical timing analysis driven post-silicon-tunable clock-tree synthesis,” in Proceedings of the 2005 IEEE/ACM International Conference on Computer Aided Design, Nov. 2005, pp. 575–581.
  • J. P. Fishburn, “Clock skew optimization,” IEEE Transactions on Computers, vol. 39, no. 7, pp. 945–951, Jul. 1990.
  • J. Kim, D. Joo, and T. Kim, “Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modes,” Integration, the VLSI journal, vol. 52, no. Supplement C, pp. 91–101, Jan. 2016.
  • J. Kim, D. Joo, and T. Kim, “An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem,” in Proceedings of the 50th IEEE/ACM Design Automation Conference, Jun. 2013, pp. 1–6.
  • J. Kim and T. Kim, “Useful clock skew scheduling using adjustable delay buffers in multi-power mode designs,” in Proceedings of the 2015 IEEE Asia and South Pacific Design Automation Conference, Jan. 2015, pp. 466–471.
  • J. Kim and T. Kim, “Adjustable delay buffer allocation under useful clock skew scheduling,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 4, pp. 641–654, Apr. 2017.
  • J. G. Xi and W. W.-M. Dai, “Useful-skew clock routing with gate sizing for low power design,” in Proceedings of the 33rd IEEE/ACM Design Automation Conference, Jun. 1996, pp. 51–67.
  • J. Cong, C.-K. Koh, and K.-S. Leung, “Simultaneous buffer and wire sizing for performance and power optimization,” in Proceedings of the 1996 ACM/IEEE International Symposium on Low Power Electronics and Design, Aug. 1996, pp. 271–276.
  • J. Cong, A. B. Kahng, C.-K. Koh, and C.-W. A. Tsao, “Bounded-skew clock and steiner routing,” ACM Transactions on Design Automation of Electronic Systems, vol. 3, no. 3, pp. 341–388, Jul. 1998.
  • I.-M. Liu, T.-L. Chou, A. Aziz, and D. F. Wong, “Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion,” in Proceedings of the 2000 ACM International Symposium on Physical Design, May 2000, pp. 33–38.
  • H.-M. Chou, H. Yu, and S.-C. Chang, “Useful-skew clock optimization for multipower mode designs,” in Proceedings of the 2011 IEEE/ACM International Conference on Computer Aided Design, Nov. 2011, pp. 647–650.
  • G. D. Hachtel and F. Somenzi, Logic Synthesis and Verification Algorithms. Boston, MA: Springer US, 1996.
  • E. Takahashi, Y. Kasai, M. Murakawa, and T. Higuchi, “A post-silicon clock timing adjustment using genetic algorithms,” in 2003 Symposium on VLSI Circuits Digest of Technical Papers, Jun. 2003, pp. 13–16.
  • C.-W. A. Tsao and C.-K. Koh, “Ust/dme: a clock tree router for general skew constraints,” ACM Transactions on Design Automation of Electronic Systems, vol. 7, no. 3, pp. 359–379, Jul. 2002.
  • C. J. Alpert, A. Devgan, and S. T. Quay, “Buffer insertion with accurate gate and interconnect delay computation,” in Proceedings of the 36th IEEE/ACM Design Automation Conference, Jun. 1999, pp. 479–484.
  • C. C. N. Chu and D. F. Wong, “An efficient and optimal algorithm for simultaneous buffer and wire sizing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 9, pp. 1297–1304, Sep. 1999.
  • A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low-power cmos digital design,” IEEE Journal of Solid-State Circuits, vol. 27, no. 4, pp. 473–484, Apr. 1992.
  • A. B. Kahng and C.-W. A. Tsao, “Planar-dme: a single-layer zero-skew clock tree router,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 1, pp. 8–19, Jan. 1996.