박사

Write Avoidance Schemes for Non-Volatile Memory based Last-Level Cache = 비휘발성 메모리 기반의 최종 레벨 캐시를 위한 쓰기 회피 기법

Choi Ju Hee 2016년
논문상세정보
' Write Avoidance Schemes for Non-Volatile Memory based Last-Level Cache = 비휘발성 메모리 기반의 최종 레벨 캐시를 위한 쓰기 회피 기법' 의 주제별 논문영향력
논문영향력 선정 방법
논문영향력 요약
주제
  • 응용 물리
  • Cache coherence
  • Cache memories
  • Cache partitioning
  • Heterogeneous (hybrid) memory systems
  • Low-power design
  • emergingtechnologies
동일주제 총논문수 논문피인용 총횟수 주제별 논문영향력의 평균
4,666 0

0.0%

' Write Avoidance Schemes for Non-Volatile Memory based Last-Level Cache = 비휘발성 메모리 기반의 최종 레벨 캐시를 위한 쓰기 회피 기법' 의 참고문헌

  • “The intel 64 and ia-32 architectures software developer’s manual.” http://www.intel.com/content/dam/www/public/us/en/documents/ manuals/64-ia-32-architectures-software-developer-systemprogramming- manual-325384.pdf. accessed 3-Mar-2014.
  • “Arm cortex-a57 processor.” ”http://www. arm.com/products/processors/cortex-a/ cortex-a57-processor.php” (accessed 1-Sep-2015).
  • Z. Wang, D. A. Jim enez, C. Xu, G. Sun, and Y. Xie, “Adaptive placement and migration policy for an stt-ram-based hybrid cache,”
  • Y.-T. Chen, J. Cong, H. Huang, C. Liu, R. Prabhakar, and G. Reinman, “Static and dynamic co-optimizations for blocks mapping in hybrid caches,” in Proceedings of International Symposium on Low Power Electronics and Design, pp. 237–242, ACM, 2012.
  • Y. Liu andW. Zhang, “Exploiting stack distance to estimate worst-case data cache performance,” in Proceedings of International Symposium on Applied Computing, pp. 1979–1983, ACM, 2009.
  • Y. Li, Y. Zhang, H. Li, Y. Chen, and A. K. Jones, “C1c: A configurable, compiler-guided stt-ram l1 cache,” ACM Transactions on Architecture and Code Optimization, vol. 10, no. 4, p. 52, 2013.
  • Y. Li, Y. Chen, and A. K. Jones, “A software approach for combating asymmetries of non-volatile memories,” in Proceedings of International Symposium on Low Power Electronics and Design, pp. 191– 196, ACM, 2012.
  • X. Wu, J. Li, L. Zhang, E. Speight, and Y. Xie, “Power and performance of read-write aware hybrid caches with non-volatile memories,” in Proceedings of International Conference on Design, Automation and Test in Europe, pp. 737–742, IEEE, 2009.
  • X. Wu, J. Li, L. Zhang, E. Speight, R. Rajamony, and Y. Xie, “Hybrid cache architecture with disparate memory technologies,” in ACM SIGARCH Computer Architecture News, vol. 37, pp. 34–45, ACM, 2009.
  • X. Dong, C. Xu, Y. Xie, and N. P. Jouppi, “Nvsim: A circuit-level performance, energy, and area model for emerging nonvolatile memory,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 7, pp. 994–1007, 2012.
  • W. Zhang and T. Li, “Exploring phase change memory and 3d diestacking for power/thermal friendly, fast and durable memory architectures,” in Proceedings of International Conference on Parallel Architectures and Compilation Techniques, pp. 101–112, IEEE, 2009.
  • T. Sumi, Y. Judai, K. Hirano, T. Ito, T. Mikawa, M. Takeo, M. Azuma, S.-i. Hayashi, Y. Uemoto, K. Arita, et al., “Ferroelectric nonvolatile memory technology and its applications,” Japanese Journal of Applied Physics, vol. 35, no. 2S, p. 1516, 1996.
  • S.-M. Syu, Y.-H. Shao, and I.-C. Lin, “High-endurance hybrid cache design in cmp architecture with cache partitioning and access-aware policy,” in Proceedings of International Conference on Great Lakes Symposium on VLSI, pp. 19–24, ACM, 2013.
  • S. Lee, K. Kang, and C.-M. Kyung, “Runtime thermal management for 3-d chip-multiprocessors with hybrid sram/mram l2 cache,” IEEE Transactions on Very Large Scale Integration Systems, vol. 23, no. 3, pp. 520–533, 2014.
  • R. L. Mattson, J. Gecsei, D. R. Slutz, and I. L. Traiger, “Evaluation techniques for storage hierarchies,” IBM Systems journal, vol. 9, no. 2, pp. 78–117, 1970.
  • Q. Li, M. Zhao, C. J. Xue, and Y. He, “Compiler-assisted preferred caching for embedded systems with stt-ram based hybrid cache,” ACM SIGPLAN Notices, vol. 47, no. 5, pp. 109–118, 2012.
  • P. Zhou, B. Zhao, J. Yang, and Y. Zhang, “Energy reduction for sttram using early write termination,” in Proceedings of International Conference on Computer-Aided Design-Digest of Technical Papers, pp. 264–268, IEEE, 2009.
  • N. Yamada, E. Ohno, K. Nishiuchi, N. Akahira, and M. Takao, “Rapidphase transitions of gete-sb2te3 pseudobinary amorphous thin films for an optical disk memory,” Journal of Applied Physics, vol. 69, no. 5, pp. 2849–2856, 1991.
  • N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, “Cacti 6.0: A tool to model large caches,” HP Laboratories, pp. 22–31, 2009.
  • N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, et al., “The gem5 simulator,” ACM SIGARCH Computer Architecture News, vol. 39, no. 2, pp. 1–7, 2011.
  • M. Zhou, Y. Du, B. Childers, R. Melhem, and D. Moss e, “Writebackaware partitioning and replacement for last-level caches in phase change main memory systems,” ACM Transactions on Architecture and Code Optimization, vol. 8, no. 4, p. 53, 2012.
  • M. K. Qureshi, V. Srinivasan, and J. A. Rivers, “Scalable high performance main memory system using phase-change memory technology,” ACM SIGARCH Computer Architecture News, vol. 37, no. 3, pp. 24–33, 2009.
  • M. K. Qureshi, M. M. Franceschini, and L. A. Lastras-Monta˜no, “Improving read performance of phase change memories via write cancellation and write pausing,” in Proceedings of International Symposium on High Performance Computer Architecture, pp. 1–11, IEEE, 2010.
  • M. K. Qureshi, D. N. Lynch, O. Mutlu, and Y. N. Patt, “A case for mlp-aware cache replacement,” ACM SIGARCH Computer Architecture News, vol. 34, no. 2, pp. 167–178, 2006.
  • M. K. Qureshi and Y. N. Patt, “Utility-based cache partitioning: A lowoverhead, high-performance, runtime mechanism to partition shared caches,” in Microarchitecture, IEEE/ACM International Symposium on, pp. 423–432, IEEE Computer Society, 2006.
  • M. Hosomi, H. Yamagishi, T. Yamamoto, K. Bessho, Y. Higo, K. Yamane, H. Yamada, M. Shoji, H. Hachino, C. Fukumoto, et al., “A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-ram,” in Proceedings of IEEE International Electron Devices Meeting, pp. 459–462, IEEE, 2005.
  • L. Eeckhout, “Computer architecture performance evaluation methods,” Synthesis Lectures on Computer Architecture, vol. 5, no. 1, pp. 1– 145, 2010.
  • K. Qiu, M. Zhao, C. Fu, L. Shi, and C. J. Xue, “Migration-aware loop retiming for stt-ram based hybrid cache for embedded systems,” in Proceedings of International Conference on Application-Specific Systems, Architectures and Processors, pp. 83–86, IEEE, 2013.
  • J. Wang, Y. Tim, W.-F. Wong, Z.-L. Ong, Z. Sun, and H. H. Li, “A coherent hybrid sram and stt-ram l1 cache architecture for shared memory multicores.,” in Proceeding of Asia and South Pacific Design Automation Conference, pp. 610–615, IEEE, 2014.
  • J. Wang, X. Dong, Y. Xie, and N. P. Jouppi, “i 2 wap: Improving non-volatile cache lifetime by reducing inter-and intra-set write vari- ations,” in Proceedings of International Symposium on High Performance Computer Architecture, pp. 234–245, IEEE, 2013.
  • J. Meza, J. Chang, H. Yoon, O. Mutlu, and P. Ranganathan, “Enabling efficient and scalable hybrid memories using fine-granularity dram cache management,” Computer Architecture Letters, vol. 11, no. 2, pp. 61–64, 2012.
  • J. Li, L. Shi, C. J. Xue, C. Yang, and Y. Xu, “Exploiting set-level write non-uniformity for energy-efficient nvm-based hybrid cache,” in Proceedings of International Symposium on Embedded Systems for Real- Time Multimedia, pp. 19–28, IEEE, 2011.
  • J. Li, C. J. Xue, and Y. Xu, “Stt-ram based energy-efficiency hybrid cache for cmps,” in Proceedings of International Conference on VLSI and System-on-Chip, pp. 31–36, IEEE, 2011.
  • J. L. Henning, "SPEC CPU2006 benchmark descriptions," ACM SIGARCH Computer Architecture News, vol. 34, no. 4, pp. 1-17, 2006.
  • J. L. Hennessy and D. A. Patterson, Computer architecture: a quantitative approach. 2011.
  • J. H. Choi, J. W. Kwak, and C. S. Jhon, “Write avoidance cache coherence protocol for non-volatile memory as last-level cache in chip-multiprocessor,” IEICE Transactions on Information and Systems, vol. 97, no. 8, pp. 2166–2169, 2014.
  • J. H. Choi, J. W. Kwak, S. T. Jhang, and C. S. Jhon, “Adaptive cache compression for non-volatile memories in embedded system,” in Proceedings of International Conference on Research in Adaptive and Convergent Systems, pp. 52–57, ACM, 2014.
  • J. H. Choi and G. H. Park, “Demand-aware nvm capacity management policy for hybrid cache architecture,” Computer Journal, advance online publication, 2015, doi:10.1093/comjnl/bxv103.
  • J. Ahn, S. Yoo, and K. Choi, “Write intensity prediction for energyefficient non-volatile caches,” in Proceedings of International Symposium on Low Power Electronics and Design, pp. 223–228, IEEE, 2013.
  • H. Yoon, J. Meza, R. Ausavarungnirun, R. A. Harding, and O. Mutlu, “Row buffer locality aware caching policies for hybrid memories,” in Proceedings of International Conference on Computer Design, pp. 337–344, IEEE, 2012.
  • H. Seok, Y. Park, and K. H. Park, “Migration based page caching algorithm for a hybrid main memory of dram and pram,” in Applied Computing, International Symposium on, pp. 595–599, ACM, 2011.
  • H. Patil, R. Cohn, M. Charney, R. Kapoor, A. Sun, and A. Karunanidhi, “Pinpointing representative portions of large intel itanium programs with dynamic instrumentation,” in Proceedings of International Symposium on Microarchitecture, pp. 81–92, IEEE Computer Society, 2004.
  • H. P.Wong, S. Raoux, S. Kim, J. Liang, J. P. Reifenberg, B. Rajendran, M. Asheghi, and K. E. Goodson, “Phase change memory,” Proceedings of the IEEE, vol. 98, no. 12, pp. 2201–2227, 2010.
  • H. Kim, J. Lee, N. B. Lakshminarayana, J. Sim, J. Lim, and T. Pho, “Macsim: A cpu-gpu heterogeneous simulation framework user guide,” Georgia Institute of Technology, 2012.
  • H. Akinaga and H. Shima, “Resistive random access memory (reram) based on metal oxides,” Proceedings of the IEEE, vol. 98, no. 12, pp. 2237–2251, 2010.
  • G. Sun, X. Dong, Y. Xie, J. Li, and Y. Chen, “A novel architecture of the 3d stacked mram l2 cache for cmps,” in Proceedings of International Symposium on High Performance Computer Architecture, pp. 239–249, IEEE, 2009.
  • G. E. Suh, L. Rudolph, and S. Devadas, “Dynamic partitioning of shared cache memory,” The Journal of Supercomputing, vol. 28, no. 1, pp. 7–26, 2004.
  • G. Dhiman, R. Ayoub, and T. Rosing, “Pdram: a hybrid pram and dram main memory system,” in Proceedings of Internaional Conference on Design Automation Conference, pp. 664–669, IEEE, 2009.
  • D. J. Sorin, M. D. Hill, and D. A. Wood, “A primer on memory consistency and cache coherence,” Synthesis Lectures on Computer Architecture, vol. 6, no. 3, pp. 1–212, 2011.
  • C.-K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S.Wallace, V. J. Reddi, and K. Hazelwood, “Pin: building customized program analysis tools with dynamic instrumentation,” in ACM Sigplan Notices, vol. 40, pp. 190–200, ACM, 2005.
  • C. CaBcaval and D. A. Padua, “Estimating cache misses and locality using stack distances,” in Proceedings of International Conference on Supercomputing, pp. 150–159, ACM, 2003.
  • C. Bienia, S. Kumar, J. P. Singh, and K. Li, “The parsec benchmark suite: Characterization and architectural implications,” in Proceedings of International Conference on Parallel Architectures and Compilation Techniques, pp. 72–81, ACM, 2008.
  • B. Quan, T. Zhang, T. Chen, and J. Wu, “Prediction table based management policy for stt-ram and sram hybrid cache,” in Proceedings of International Conference on Computing and Convergence Technology, pp. 1092–1097, IEEE, 2012.
  • A. Snavely and D. M. Tullsen, “Symbiotic jobscheduling for a simultaneous mutlithreading processor,” ACM SIGPLAN Notices, vol. 35, no. 11, pp. 234–244, 2000.
  • A. Samih, Y. Solihin, and A. Krishna, “Evaluating placement policies for managing capacity sharing in cmp architectures with private caches,” ACM Transactions on Architecture and Code Optimization, vol. 8, no. 3, p. 15, 2011.
  • A. P. Ferreira, M. Zhou, S. Bock, B. Childers, R. Melhem, and D. Moss e, “Increasing pcm main memory lifetime,” in Proceedings of Internaional Conference on Design, Automation and Test in Europe, pp. 914–919, IEEE, 2010.
  • A. Jadidi, M. Arjomand, and H. Sarbazi-Azad, “High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement,” in Proceedings of International Symposium on Low Power Electronics and Design, pp. 79–84, IEEE, 2011.
  • A. Driskill-Smith, S. Watts, D. Apalkov, D. Druist, X. Tang, Z. Diao, X. Luo, A. Ong, V. Nikitin, and E. Chen, “Non-volatile spin-transfer torque ram (stt-ram): An analysis of chip data, thermal stability and scalability,” in Proceedings of IEEE International Memory Workshop, pp. 1–3, IEEE, 2010.