박사

밀리미터파 PLL의 고출력 전압 제어 발진기와 고해상도 시간 디지털 변환기의 연구 = A Study on the High Power VCO and the High Resolution TDC for mm-Wave PLL

이종석 2015년
논문상세정보
    • 저자 이종석
    • 형태사항 26 cm: 삽화, 도표: xii, 111 p.
    • 일반주기 숭실대학교 논문은 저작권에 의해 보호받습니다, 지도교수: 문용, 참고문헌: p. 103-111
    • 학위논문사항 전자공학과, 숭실대학교 대학원, 2016. 2, 학위논문(박사)-
    • DDC 23, 621.381
    • 발행지 서울
    • 출판년 2015
    • 발행사항 숭실대학교 대학원
    • 주제어 TDC VCO
    유사주제 논문( 41)
' 밀리미터파 PLL의 고출력 전압 제어 발진기와 고해상도 시간 디지털 변환기의 연구 = A Study on the High Power VCO and the High Resolution TDC for mm-Wave PLL' 의 주제별 논문영향력
논문영향력 선정 방법
논문영향력 요약
주제
  • tdc
  • vco
동일주제 총논문수 논문피인용 총횟수 주제별 논문영향력의 평균
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' 밀리미터파 PLL의 고출력 전압 제어 발진기와 고해상도 시간 디지털 변환기의 연구 = A Study on the High Power VCO and the High Resolution TDC for mm-Wave PLL' 의 참고문헌

  • 시간-디지털 변환기의 성능에 관한 연구,
    문용 안태원 이종석 대한전자공학회 논문지 49권 IE편 제 호, pp.1-6, 년 3월 [2012]
  • 버니어 지연을 이용한 2단 시간 증폭기의 연구”
    문용 이종석 대한전자공학회 하계종합학술대회, 2009년 7월 [2009]
  • 버니어 3단 시간 디지털 변환기의 연구
    문용 이종석 SoC학술대회, pp.336~339, 2011년 4월 [2011]
  • “차량용 레이더 센서의 현황 및 연구개발 동향,”
    민경원 손행선 전자공학회지, Vol.40, No.6, pp.28-38, 년 6월 [2013]
  • “밀리미터파 개념 및 동향,”
    윤두영 정보통신정책, Vol.18, No.14,pp.52-56, 년 8월 [2006]
  • “60GHz 주파수 대역 기반 밀리미터파 무선전송기술 표준화 동향,”
    이우용 정현규 홍승은 TTA 저널, No.130 pp.87-92, 년 7월 [2010]
  • “13bit의 해상도를 갖는 3단 시간 디지털 변환기의연구”
    문용 이종석 제 20회 반도체학술대회, 년 2월 [2013]
  • he-Yang Huang, “A 57.15?59.00GHz CMOS LC-VCO forV-Band high speed WPAN communication system,” IEEEEuMC, pp.671-673, Oct. 2011.
  • Zule Xu, Seungjong Lee, Miyahara, M., and Matsuzawa, A.,“A 0.84ps-LSB 2.47mW time-to-digital converter using chargepump and SAR-ADC,” IEEE Custom Integrated CircuitsConference, pp.1-4, Sept. 2013.
  • Zhouyue Pi and Farooq Khan, “An Introduction to Millimeter-WaveMobile Broadband Systems,” IEEE Communications Magazine,Vol.49, No.6, pp.101-107, Jun. 2011.
  • Zhe-Yang Huang, “A 57.15?59.00GHz CMOS LC-VCO forV-Band high speed WPAN communication system,” IEEE RFIC,pp.127-130, Apr. 2008.
  • Zhe-Yang Huang*, # and Chung-Chih Hun, “1V 4.8mW42.6-45.6GHz CMOS Voltage Controlled Oscillator for IEEE802.15.3c wireless communication system,” IEEE APMC,pp.485-487, Dec. 2010.
  • Yu-Li Hsueh, Lan-Chou Cho, Chih-Hsien Shen, Yi-Chien Tsai,Tzu-Chan Chueh, Tao-Yao Chang, Jui-Lin Hsu, and Jing-HongConan Zhan, “28.2 A 0.29mm2 frequency synthesizer in 40nmCMOS with 0.19psrms jitter and <-100dBc reference spur for802.11ac,” IEEE ISSCC, pp.472-473, Feb. 2014.
  • Yu-Hsuan, Lin, Jeng-Han Tsai, Yen-Hung Kuo, and Tian-WeiHuang, “An ultra low-power 24 GHz Phase-lock-loop with lowphase-noise VCO embedded in 0.18㎛ CMOS process,” IEEEAPMC, pp.1630-1633, Dec. 2011.
  • Ying. Cao, Leroux, P., De Cock, W., Steyaert, M., “1.7㎽ 11b1-1-1 MASH ΔΣTime-to-Digital Converter,” ISSCC, Dig. Tech.Papers, pp.480-481, Feb. 2011.
  • Xiaolu Liu, Na Yan, Xi Tan, and Hao Min, “A 0.8psminimum-resolution sub-exponent TDC for ADPLL in 0.13 ㎛CMOS,” IEEE Annual Conference of The Association ofSurgeons of India (ASICON), pp.602- 605, Oct. 2011.
  • Xiang Yi, Chirn Chye Boon, Hang Liu, Jia Fu Lin, Jian ChengOng, and Wei Meng Lim, “A 57.9-to-68.3GHz 24.6mW frequencysynthesizer with in-phase injection-coupled QVCO in 65nmCMOS,” IEEE ISSCC, pp.354-355, Feb. 2013.
  • Xiang Gao, Luns Tee, Wanghua Wu, Kun-Seok Lee, ArvindAnumula Paramanandam, Anuranjan Jha, Norman Liu, EdwinChan, and Li Lin9.4, “A 28nm CMOS digital fractional-N PLLwith 245.5dB FOM and a frequency ? tripler for 802.11abgn/acradio,” IEEE ISSCC, pp.166-167, Feb. 2015.
  • Wei Fei, HaoYu, Haipeng Fu, Junyan Ren, and Kiat Seng Yeo,“Design and Analysis of Wide Frequency-Tuning-Range CMOS60 GHz VCO by Switching Inductor Loaded Transformer,” Circuitand Systems I: regular papers, IEEE Transactions on (TCSI), vol.61, no. 3, pp. 699-711, 2014.
  • Vishal P. Trivedi and Kun-Hin To, “A Novel mmWave CMOSVCO with an AC-Coupled LC Tank,” IEEE, Radio FrequencyIntegrated Circuits Symposium (RFIC),pp. 515-518, Jun. 2012.
  • Viki Szortyka, Qixian Shi, Kuba Raczkowski, Bertrand Parvais,Maarten Kuijk, and Piet Wambacq, “A 42mW 230fs-jittersub-sampling 60GHz PLL in 40nm CMOS, IEEE ISSCC,pp.366-367, Feb. 2014.
  • Tzuen-Hsi Huang and Pen-Li Yo, “27-GHz low phase-noiseCMOS standing-wave oscillator for millimeter waveapplications,” IEEE MWSYM, pp.367-370, Jun. 2008.
  • Tsung-Hsien Tsai, Min-Shueh Yuan, Chih-Hsien Chang,hia-Chun Liao, Chao-Chieh Li, and Robert Bogdan Staszewski,“A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in16nm FinFET CM0S,” IEEE ISSCC, pp.260-261, Feb. 2015.
  • Thomas H. LEE, The Design of CMOS Radio-FrequencyIntegrated circuits, 2nd ed. CAMBRIDGE, 2004.
  • Shiyou Zhao, Kaushik Roy, and Cheng-Kok Koh, “Decouplingcapacitance allocation and its application to power-supplynoise-aware floorplanning,”IEEE Computer-Aided Design ofIntegrated Circuits and Systems, Vol.21, No.1, PP.81-92, Jan. 2002.
  • Sedra, Microelectronic Circuits, 5th ed. Oxford, Dec. 2013.
  • Samarah, A., and Carusone, A.C., “A Digital Phase-Locked LoopWith Calibrated Coarse and Stochastic Fine TDC,” IEEEJ.Solid-State Circuits, Vol.48, No.8, pp.1829-1841, Aug. 2013.
  • S. Henzler, S. Koeppe, D. Lorenz, W. Kamp, R. Kuenemund, andD. Schmitt-Landsiedel, “Variation tolerant high resolution andlow latency time-to-digital converter,” IEEE ESSCIRC,pp.194-197, Sep. 2007.
  • Rohde, U. L. and D. P. Newkirk, RF/Microwave Circuit Designfor Wireless Applications, Wiley Interscience, 2000.
  • Qiong Zou, Student Member, Kaixue Ma, Senior Member, andKiat Seng Yeo, “A Low Phase Noise and Wide Tuning RangeMillimeter-Wave VCO Using Switchable CoupledVCO-Cores,”IEEE TCSⅠ, Vol.62, No.2, pp.554-563, Feb. 2015.
  • Ping Lu, Member, Antonio Liscidini, and Pietro Andreani, “A3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital ConverterWith an Equivalent Resolution of 3.2 ps,” IEEE JSSC, Vol.47,No.7, pp.1626-1635, Jul. 2012.
  • NIPA 간행물, “밀리미터파 레이더 양산, 차량 충돌방지시스템 대중화 기대
    ” 정보통신기술진흥센터, pp.36-39, 년 10월 [2014]
  • Minyoung Song, Taeik Kim, Jihyun Kim, Wooseok Kim,Sung-Jin Kim, Hojin Park, “14.8 A 0.009mm2 2.06mW32-to-2000MHz 2nd-order ΔΣ analogous bang-bang digital PLLwith feed-forward delay-locked and phase-locked operations in14nm FinFET technology,” IEEE ISSCC, pp.266-267, Feb. 2015.
  • Minjae Lee and Asad A. Abidi, “A9 b, 1.25 ps ResolutionCoarse?Fine Time-to-Digital Converter in 90 nm CMOS thatAmplifies a Time Residue,” IEEE JSSC, Vol.43, No.4, pp.769-777,Apr. 2008.
  • Liang Wu, Howard C. Luong, “A 49-to-62GHz CMOSQuadrature VCO with Bimodal Enhanced Magnetic Tuning,” inProc. ESSCIRC, pp.297?300, Sept. 2012.
  • Kuo-Hsing Chenf, Chang-Chien Hu, Jen-Chieh Liu, Hong-YiHuang, “A Time-to-Digital Converter Using Multi-Phase-Sampling and Time Amplifier for All Digital Phase-LockdeLoop,” IEEE DDECS, pp.285-288, Apr. 2010.
  • Jaewon Choi1, Duwon Jung, and Chulhun Seo, “Low PhaseNoise VCO using microstrip square open loop split ringresonator,” IEEE APMC, pp.1-4, Dec. 2008.
  • Ja-Yol Lee, Haecheon Kim, and Hyun-Kyu Yu, “A 52GHzMillimeter-Wave PLL Synthesizer for 60GHz WPAN Radio,”IEEE EuMIC, pp.155-158, Oct. 2008.
  • Hyung Seok Kim, Carlos Ornelas, Kailash Chandrashekar, DanShi, Pin-en Su, Paolo Madoglio, William Y. Li, Member, andAshoke Ravi, “Digital Fractional-N PLL With a PVT andMismatch Insensitive TDC Utilizing Equivalent Time SamplingTechnique, ” IEEE JSSC, Vol.48, No.7, pp.1721-1729, Apr. 2013.
  • Hyojun Kim, Jinwoo Sang, Hyunik Kim, Youngwoo Jo, TaeikKim, Hojin Park, and SeongHwan Cho1“A 5GHz ?95dBc-reference-Spur 9.5mW digital fractional-N PLL using referencemultipliedtime-to-digital converter and reference-spur cancellationin 65nm CMOS,” IEEE ISSCC, pp.258-259, Feb. 2015.
  • Hsieh-Hung Hsieh and Liang-Hung Lu, “A 63-GHz voltagecontrolledoscillator in 0.18-㎛ CMOS,”IEEE VLSIC, pp.178-179,Jun. 2007.
  • Hayun Chung, Hiroki Ishikuro, and Tadahiro Kuroda, “A 10-Bit80-MS/s Decision-Select Successive Approximation TDC in65-nm CMOS, IEEE JSSC, Vol.47, No.5, pp.1232-1241, May. 2012.
  • Haikun Jia, Baoyong Chi, Lixue Kuang, and Zhihua Wang, “A47.6 71.0-GHz 65-nm CMOS VCO Based ? on Magnetically Coupled-Type LC Network,” IEEE, Transactions on Microwave Theoryand Techniques (TMTT), Vol.63, No.5, pp.1645-1657, May. 2015.
  • Domenico Pepe and Domenico Zito, “A compact 67 GHzoscillator in 65nm CMOS,” IEEE NWECAS, pp.1-4, Jun. 2015.
  • Cisco Visual Networking Index: Global Mobile Data TrafficForecast Update 2014?2019 White Paper, 2015. (http://www.cisco.com/c/en/us/solutions/collateral/service-provider/visual-networking-index-vni/white_paper_c11-520862.html)
  • Chihun Lee, Lan-Chou Cho, Jia-Hao Wu, and Shen-Iuan Liu, “A50.8?53-GHz Clock Generator Using a Harmonic-Locked PD in0.13-㎛ CMOS,” IEEE TCSⅡ, Vol55. No.5, pp.404-408, May.2008.
  • Che-Chen Lee, Shu-Yan Huang, and Hong-Y eh Chang, “A44-49 GHz Low Phase Noise CMOS Voltage-Controlled Oscillatorwith 10-dBm Output Power and 16.1 % Efficiency,” MicrowaveSymposium (IMS), 2014 IEEE MTT-S International,pp.1-4,Jun.2014.
  • Changhua Cao, Yanping Ding, and Kenneth K. O, “A 50-GHzPhase-Locked Loop in 130-nm CMOS, IEEE CICC, pp.21-24, Sep.2006.
  • Changhua Cao, Yanping Ding, Kenneth K. O, “A 50-GHzPhase-Locked Loop in 0.13-㎛ CMOS, IEEE JSSC, Vol.42, No.8,pp.1649-1656, Aug. 2007.
  • Changhua Cao and Kenneth K.O., “Millimeter-wave voltagecontrolledoscillators in 0.13-μm MOS technology,” IEEE, J.Solid-State Citcuits (JSSC), Vol.41, No.6, pp.1297-1304, Jun. 2006.
  • Bodhisatwa Sadhu, Mark Ferriss, and Alberto Valdes-Garcia, “A52 GHz Frequency Synthesizer Featuring a 2nd HarmonicExtraction Technique That Preserves VCO Performance,” IEEE,J. Solid-State Circuits (JSSC), Vol.50, No.5, pp.1214-1223, May.2015.
  • Bodhisatwa Sadhu, Mark Ferriss, Alberto Valdes-Garcia, “A46.4 58.1 GHz Frequency Synthesizer ? Featuring a 2nd HarmonicExtraction Technique that Preserves VCO Performance,” IEEERFIC, pp.173-176, Jun. 2014.
  • Behzad Razavi, Design of Analog CMOS Integrated Circuits,McGRAW-HILL INTERNATIONAL EDITION, 2001.
  • Amr Elshazly, Sachin Rao, Brian Young, and Pavan KumarHanumolu, “A 13b 315fsrms 2mW 500MS/s 1MHz BandwidthHighly Digital Time-to-Digital Converter Using Switched RingOscillators,” IEEE ISSCC, pp.464-465, Feb. 2012.
  • Alan Hastings, The Art of ANALOG LAYOUT, 2nd ed, PearsonInternational Edition, 2006.
  • A. M. Abas, G. Russell, and D. J. Kinniment, “Design of sub10-picoseconds on-chip time measurement circuit,” in Proc.Design Automation Test Europe Conf., vol. 2, pp. 804?809, 2004.