'
Design of high-performance delta-sigma modulator for wideband analog-to-digital conversion' 의 주제별 논문영향력
논문영향력 요약
주제
analog-to-digital converter
delta-sigma modulator
wideband
동일주제 총논문수
논문피인용 총횟수
주제별 논문영향력의 평균
78
0
0.0%
주제별 논문영향력
논문영향력
주제
주제별 논문수
주제별 피인용횟수
주제별 논문영향력
주제어
analog-to-digital converter
20
0
0.0%
delta-sigma modulator
12
0
0.0%
wideband
46
0
0.0%
계
78
0
0.0%
* 다른 주제어 보유 논문에서 피인용된 횟수
0
'
Design of high-performance delta-sigma modulator for wideband analog-to-digital conversion' 의 참고문헌
Z. Sohrabi and M. Yavari A 13 bit 10 MHz bandwidth MASH 3-2 modulator in 90 nm CMOS, International Journal of Circuit Theory andApplications, vol. 41, no. 11, pp. 1136?1153, Aug. 2013.
Y. L. Guillou, Analyzing sigma-delta adcs in deep-submicron CMOStechnologies, [Online]. Available: http://defenseelectronicsmag.com/sitefiles/defenseelectronicsmag.com/files/archive/rfdesign.com/ar/502rfdf1.pdf.
Y. Ke, P. Gao, J. Craninckx, G. Van der Plas, and G. Gielen, A 2.8-to-8.5mW GSM/Bluetooth/UMTS/DVB-H/WLAN fully reconfigurable CT with 200kHz to 20MHz BW for 4G radios in 90nm digital CMOS, in Symposiumon VLSI Circuits, Jun. 2010, pp. 153-154.
Y. Jung, H. Roh, and J. Roh, An input-feedforward multibit adder-less - modulator for ultrasound imaging systems, IEEE Trans. Instrum. Meas.,vol. 62, no. 8, pp. 2215?2227, Aug. 2013.
Y. Geerts, M. Steyaert, and W. Sansen, Design of Multi-bit Delta-Sigma A/DConverters, Kluwer Acadamic Publishers, 2002.
Y. Chae, and G. Han, Low voltage, low power, inverter-based switchedcapacitordelta-sigma modulator, IEEE Journal of Solid-State Circuits, vol.44, no. 2, pp. 458-472, Feb. 2009.
Y. Chae, J. Cheon, S. Lim, M. Kwon, K. Yoo, W. Jung, D. Lee, S. Ham, andG. Han, A 2.1 M pixels, 120 frame/s CMOS image sensor with columnparallel ADC architecture. IEEE Journal of Solid-State Circuits, vol.46, no. 1, pp. 236-247, Jan. 2011.
X. Meng, Y. Zhang, T. He and G. C. Temes, Low-distortion wideband deltasigmaADCs with shifted loop delays, IEEE Trans. Circuits Syst. I, vol. 62,no. 2, pp. 376?384, Feb. 2015.
What Is Data Acquisition?, National Instruments Inc. [Online]. Available:http://www.ni.com/data-acquisition/what-is/
T.-H. Chang and L.-R. Dung, Fourth-order cascaded modulator usingtri-level quantization and bandpass noise shaping for broadband telecommunicationapplications, IEEE Trans. Circuits Syst. I, vol. 55, no. 6, pp.1722?1732, Jul. 2008.
T. Nagai, H. Satou, H. Yamazaki, and Y. Watanabe, A 1.2V 3.5mW modulator with a passive current summing network and a variable gain function, in ISSCC digest of technical papers, Feb. 2005, pp. 494-495.
T. Christen, and Q. Huang, A 0.13 m CMOS 0.1-20MHz bandwidth 86-70dB DR multi-mode DT ADC for IMT-Advanced, in ESSCIRC, Sept.2010, pp. 414?417.
T. Christen, T. Burger, and Q. Huang, A 0.13 m CMOSEDGE/UMTS/WLAN tri-mode ADC with -92dB THD, in ISSCCDig. Tech. Papers, Feb. 2007, pp. 240?241.79
T. Christen, A 15bit 140 W scalable-bandwidth inverter-based audio modulator with >78dB PSRR, in Proceeding of ESSCIRC , Sep. 2012, pp.209-212.
S.-H. Wu and J.-T. Wu, A 81-dB dynamic range 16-MHz bandwidth modulator using background calibration, IEEE J. Solid-State Circuits, vol.48, no. 9, pp. 2170?2179, Sept. 2013.
S.-C. Lee and Y. Chiu, A 15-MHz bandwidth 1-0 MASH ADC withnonlinear memory error calibration achieving 85-dBc SFDR, IEEE J. Solid-State Circuits, vol. 49, no. 3, pp. 695?707, Mar. 2014.
S. Zaliasl, S. Saxena, P. K. Hanumolu, K. Mayaram, and T. S. Fiez, A12.5-bit 4 MHz 13.8 mW MASH modulator with multirated VCO-basedADC, IEEE Trans. Circuits Syst. I, vol. 59, no. 8, pp. 1604?1613, Aug.2012.
S. Rabii and Bruce A. Wooley, The Design of Low-voltage, Low-powerSigma-Delta Modulators, Kluwer Acadamic Publishers, 1999.81
S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data Converters:Theory, Design, and Simulation, New York: Wiley-IEEE Press, 1996.
S. Guo and H. Lee, Single-capacitor active-feedback compensation forsmall-capacitive-load three-stage amplifiers, IEEE Transactions on Circuitsand Systems-II, vol. 56, no. 10, pp. 758-762, Oct. 2009.
Rapidly Developing a Portable, Low-Cost In-Vehicle Data Acquisition SystemUsing LabVIEW and NI Data Acquisition Hardware, National InstrumentsInc. [Online]. Available: http://sine.ni.com/cs/app/doc/p/id/cs-12694
R.J. Babita, T.K. Shahana, and P. Mythili, Wideband low-distortion sigmadeltaADC for WLAN with rns based decimation filter, in Proceedings ofthe IET-UK International Conference on Information and CommunicationTechnology in Electrical Sciences (ICTES), pp. 546?552, 2007
R. Zanbaghi, S. Saxena, G. C. Temes, and T. S. Fiez, A 75-dB SNDR, 5-MHz bandwidth stage-shared 2-2 MASH modulator dissipating 16 mWpower, IEEE Trans. Circuits Syst. I, vol. 59, no. 8, pp. 1614?1625, Aug.2012.
R. T. Baird and T. S. Fiez, Improved DAC linearity using data weightedaveraging, in IEEE Int. Symp. Circuits and Systems, Apr. 1995, vol. 1, pp.13?16.
R. T. Baird and T. Fiez, Linearity enhancement of multibit A/D and D/Aconverters using data weighted averaging, IEEE Transactions on Circuitsand Systems ?II: Analog and Digital Signal Processing., vol. 42, no. 12, pp.753?762, Dec. 1995.
R. Schreier, J. Silva, J. Steensgaard and G. C. Temes, Design-oriented estimationof thermal noise in switched-capacitor circuits, IEEE Trans. CircuitsSyst. I, vol. 52, no. 11, pp. 2358?2368, Nov. 2005.
R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters,Piscataway, NJ: IEEE Press, 2005.
R. Schreier and B. Zhang, Noise-shaped multibit D/A converter employingunit elements, IET Electronics Letters., vol. 31, no. 20, pp. 1712?1713, Sep.1995.
R. M. Gray and D. L. Neuhoff, Quantization, IEEE Trans. InformationTheory, vol. 44, no. 6, pp. 2325?2383, Oct. 1998.
R. K. Henderson and O. J. A. P. Nys, Dynamic element matching techniqueswith arbitrary noise shaping function, in Proceedings IEEE InternationalSymposium on Circuits and Systems., Atlanta, pp. 293?296, May. 1996.
R. Jocob Baker, Harry W. Li, and David E. Boyce, CMOS Circuit Design,Layout, and Simulation, IEEE Press, 1998.
R. H. M. van Veldhoven, R. Rutten, and L. J. Breems, An inverter-basedhybrid modulator in ISSCC digest of technical papers, Feb. 2008, pp.492-493.
P. Fontaine, A. N. Mohieldin, and A. Bellaouar, A low-noise low-voltageCT modulator with digital compensation of excess loop delay, in ISSCCdigest of technical papers, Feb. 2005, pp. 498-499.
O. J. A. P. Nys and R. K. Henderson, An analysis of dynamic elementmatching techniques in sigma-delta modulation, in Proceedings IEEE InternationalSymposium on Circuits and Systems., Atlanta, pp. 231?234, May.1996.
L. R. Carley and J. Kenney, A 16-bit 4 th order noise-shaping D/A converter, in Proc. of the IEEE Custom Integrated Circuits Conference, pp.21.7.1?4, 1988.
L. Perraud, M. Recouly, C. Pinatel, N. Sornin, J.-L. Bonnot, F. Benoist,N. Massei, and O. Gibrat, A direct-conversion CMOS transceiver forthe 802.11a/b/g WLAN standard utilizing a cartesian feedback transmitter, IEEE J. Solid-State Circuit, vol. 39, no. 12, pp. 2226?2238, 2004
L. Breems and L. Huijsing, Continuous-time sigma-delta modulation for A/Dconversion in radio receivers, Springer Science & Business Media., 2001.
K.-P. Pun , S. Chatterjee and P. Kinget, A 0.5-V 74-dB SNDR 25 kHzCT modulator with return-to-open DAC, in ISSCC digest of technicalpapers, pp. 74-75, Feb. 2006.
K. Yamamoto, and A. C. Carusone, A 1-1-1-1 MASH delta-sigma modulatorwith dynamic comparator-based OTAs, IEEE J. Solid-State Circuits,vol. 47, no. 8, pp. 1866?1883, Aug. 2012.
K. Reddy and S. Pavan, Fundamental limitations of continuous-time deltasigmamodulators due to clock jitter, IEEE Trans. Circuits Syst. I, vol. 54,no. 10, pp. 2184?2194, Oct. 2007.
K. El-Sankary, H. H. Alamdari and E. I. El-Masry, An adaptive ELD compensationtechnique using a predictive comparator, IEEE Trans. CircuitsSyst. II, vol. 56, no. 8, pp. 619?623, Aug. 2009.
K. B. Klaasen, Digitally controlled absolute voltage division, IEEE Trans.Instrum. Meas., vol. 24, no. 2, pp. 106?112, June. 1975.
Jos e M. de la Rosa, and Roc o del R o, CMOS Delta-Sigma Converters:Practical Design Guide, New York: John Wiley & Sons, 2013.
J.-S. Chiang and H.-L. Chen, Opamp gain insensitive MASH sigma deltamodulator for wide bandwidth applications, Analog Integr. Circuits SignalProcess., vol. 47, no. 3, pp. 281?291, June 2006.78
J.-H Yeh, J.-C. Chen, and C.-C. Lee WLAN standards, IEEE Potentials,vol. 22, no. 4, pp. 16?22, 2003
J. Silva, U. Moon, J. Steensgaard, and G. C. Temes, Wideband lowdistortiondelta-sigma ADC topology, Electron. Lett., vol. 37, no. 12, pp.737?738, Jun. 2001.
J. Roh, S. Byun, Y. Choi, H. Roh, Y. Kim, and J. Kwon, A 0.9-V 60- W1-bit fourth-order delta-sigma modulator with 83-dB dynamic range, IEEEJournal of Solid-State Circuits, vol. 43, no. 2, pp. 361-370, Feb. 2008.
J. Roh, High-gain class-AB OTA with low quiescent current Analog IntegratedCircuits and Signal Processing, vol. 47, no. 2, pp. 225-228, Feb.2006.
J. C. Candy and G. C. Temes, Oversampling Delta-Sigma Data Converters:Theory, Design, and Simulation. New York: Wiley-IEEE Press, 1992.
H. Zare-Hoseini, I. Kale, and O. Shoaei, Modeling of switched-capacitordelta-sigma modulators in SIMULINK, IEEE Trans. Instrum. Meas., vol.54, no. 4, pp. 1646?1654, Aug. 2005.
H. Luo, Y. Han, X. Liu, G, Liang, and L. Liao, An audio cascaded modulator using gain-boost class-C inverter, in Proceeding of EDSSC, Nov.2011, pp. 1-2.80
F. Michel, and M. S. J. Steyaert, A 250 mV 7.5 W 61 dB SNDR SC modulator using near-threshold-voltage-biased inverter amplifiers in 130 nmCMOS, IEEE Journal of Solid-State Circuits, vol. 47, no. 3, pp. 709-721,Mar. 2012.
F. Medeiro, B. P erez-Verd u, and A. Rodriguez-V azquez, Top-Down Designof High-Performance Sigma-Delta Modulators. Boston, MA: Kluwer, 1999.
E. Siragusa and I. Galton, A digitally enhanced 1.8-V 15-bit 40-MSample/sCMOS pipelined ADC, IEEE Journal of Solid-State Circuits, vol. 39, no.12, pp. 2126-2138, 2004.
D. Li, Y. T. Yang, Z. C. Shi, and Y. Liu, A low-distortion multi-bitsigma?delta ADC with mismatch-shaping DACs for WLAN applications, Microelectronics Journal, vol. 46, no. 1, pp. 52?58, 2015
D. A. Johns and K, Martin, Analog Integrated Cictuit Design, New York:John Wiley & Sons, 1997.
C. W. Tsang, Y. Chiu, and B. Nikolic, A 1.2V, 10.8mW, 500kHz sigmadeltamodulator with 84dB SNDR and 96dB SFDR, in Symposium on VLSICircuits, Jun. 2006, pp. 162-163.
B. R. Carlton, H. Lakdawala, E. Alpman, J. Rizk, Y. William Li, B. Perez-Esparza, V. Rivera et al, A 32nm, 1.05V, BIST enabled, 10-40MHz, 11-9bit, 0.13mm2 digitized integrator MASH ADC, in IEEE Symp. VLSICircuits, 2011, pp. 36?37.77
B. Putter, A 5th-order CT/DT multi-mode modulator, in ISSCC digestof technical papers, Feb. 2007, pp. 244-245.
B. Murmann, ADC Performance Survey 1997-2014, [Online]. Available:http://www.stanford.edu/ murmann/adcsurvey.html.76
B. Murmann and B. Boser, A 12-bit 75-MS/s pipelined ADC using openloopresidue amplification, IEEE Journal of Solid-State Circuits, vol. 38,no. 12, pp. 2040-2050, 2003.
ADC081S051 data sheet, Texas Instruments Inc. [Online]. Available:http://www.ti.com/lit/ds/symlink/adc081s101.pdf74
A. Morgado, R. del Rio, and J. M. dela Rosa, High-efficiency cascade modulators for the next generation software-defined-radio mobile systems, IEEE Trans. Instrum. Meas., vol. 61, no. 11, pp. 2860?2869, Nov. 2012.
A. Morgado, R. del Rio, J. M. de la Rosa, L. Bos, J. Ryckaert, and G. Van derPlas, A 100kHz-10MHz BW, 78-to-52dB DR, 4.6-to-11mW flexible SC modulator in 1.2-V 90-nm CMOS, in Proc. ESSCIRC, 2010, pp. 418?421.
A. Gharbiya and D. A. Johns, On the implementation of input-feedforwarddelta-sigma modulators, IEEE Trans. Circuits Syst. II, vol. 53, no. 6, pp.453?457, Jun. 2006.
A. A. Hamoui and K. W. Martin, High-order multibit modulators andpseudo data-weighted-averaging in low-oversampling ADCs for broad-75band applications, IEEE Trans. Circuits Syst. I, vol. 51, no. 1, pp. 72?85,Jan. 2004.
'
Design of high-performance delta-sigma modulator for wideband analog-to-digital conversion'
의 유사주제(
) 논문