연구동향 분석
박사

Design Methodology for Mesh based Clock Networks : 메쉬 기반의 클락 네트워크 설계 방법론

강민석 2015년

논문상세정보
인용/피인용
' Design Methodology for Mesh based Clock Networks : 메쉬 기반의 클락 네트워크 설계 방법론' 의 주제별 논문영향력
논문영향력 선정 방법
논문영향력 요약
주제
  • clock mesh synthesis
  • resource allocation & binding
  • variation tolerance
  • vlsi & cad
동일주제 총논문수 논문피인용 총횟수 주제별 논문영향력의 평균
5 0

0.0%

' Design Methodology for Mesh based Clock Networks : 메쉬 기반의 클락 네트워크 설계 방법론' 의 참고문헌

  • Y. Zhong and M. D. F. Wong, Fast placement optimization of power supplypads, in Proceedings of the 12th Asia and South Pacific Design Automation Con-ference, Jan. 2007, pp. 763?767.
  • Y. Liu, S. R. Nassif, L. T. Pileggi, and A. J. Strojwas, Impact of interconnectvariations on the clock skew of a gigahertz microprocessor, in Proceedings ofthe ACM/IEEE Design Automation Conference, Jun. 2000, pp. 168?171.
  • X. Lu, Z. Li, W. Qui, D. M. H. Walker, and W. Shi, Longest-path selectionfor delay test under process variations, IEEE Transactions on Computer-AidedDesign of Integrated Circuits and Systems, vol. 24, no. 12, pp. 1924?1929, Dec.2005.
  • X. Hu,W. Condley, and M. R. Guthaus, Library-aware resonant clock synthesis(larcs), in Proceedings of the ACM/IEEE Design Automation Conference, Jun.2012, pp. 145?150.
  • W.-C. D. Lam, J. Jain, C.-K. Koh, V. Balakrishnan, and Y. Chen, Statisticalbased link insertion for robust clock network design, in Proceedings of theACM/IEEE International Conference on Computer-Aided Design, Nov. 2005, pp.588?591.
  • V. Wason, R. Murgai, and W. W. Walker, An efficient uncertainty- and skewawaremethodology for clock tree synthesis and analysis, in Proceedings of the20th International Conference on VLSI Design, Jan. 2007, pp. 271?277.
  • V. Tiwari, D. Singh, S. Rajgopal, G. Mehta, R. Patel, and F. Baez, Reducingpower in high-performance microprocessors, in Proceedings of the ACM/IEEEDesign Automation Conference, Jun. 1998, pp. 732?737.
  • V. S. Sathe, S. Arekapudi, A. Ishii, C. Ouyang, M. C. Papaefthymiou, and S. Naffziger, Resonant-clock design for a power-efficient high-volume x86-64 microprocessor, vol. 48, no. 1, pp. 140?149, Jan. 2013.
  • V. Mehrotra, Modeling the effect of systematic process variation on circuit performance, Ph.D. Thesis, MIT, May 2001.
  • U. Padmanabhan, J. M. Wang, and J. Hu, Robust clock tree routing in the presenceof process variations, IEEE Transactions on Computer-Aided Design of In-tegrated Circuits and Systems, vol. 27, no. 8, pp. 1385?1397, Aug. 2008.
  • T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K. D. Boese, and A. B. Kahng, Zero-skewclock routing with minimum wirelength, IEEE Transactions on Circuits andSystems, vol. 39, no. 11, pp. 799?814, Nov. 1992.
  • T. A. Davis, A column pre-ordering strategy for the unsymmetric-pattern multifrontalmethod, ACM Transactions on Mathematical Software, vol. 30, no. 2,pp. 165?195, Jun. 2004.
  • Synopsys, Hspice(R) User Guide: Simulation and Analysis. Version E-2010.12,Dec. 2010.82
  • S.M. Alam, F. L.Wei, C. L. Gan, C. V. Thompson, and D. E. Troxel, Electromigrationreliability comparison of cu and al interconnects, in Proceedings of the6th International Symposium on Quality Electronic Design (ISQED), Mar. 2005,pp. 303?308.
  • S. Zanella, A. Nardi, A. Neviani, M. Quarantelli, S. Saxena, and C. Guardiani, Analysis of the impact of process variations on clock skew, IEEE Transactionson Semiconductor Manufacturing, vol. 13, no. 4, pp. 401?407, Nov. 2000.
  • S. Bhunia and S. Mukhopadhyay, Low-Power Variation-Tolerant Design inNanometer Silicon. Springer, 2011.80
  • R.-S. Tsay, An exact zero-skew clock routing algorithm, IEEE Transactions onComputer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 2, pp.242?249, Feb. 1993.79
  • R. Mahajan, C.-P. Chiu, and G. Chrysler, Cooling a microprocessor chip, Pro-ceedings of the IEEE, vol. 94, no. 8, pp. 1476?1486, Aug. 2006.
  • R. J. Restle and et al., A clock distribution network for microprocessors, IEEEJournal of Solid-State Circuits, vol. 36, no. 5, pp. 792?799, May 2001.
  • R. Bhutada and Y. Manoli, Complex clock gating with integrated clock gatinglogic cell, in Proceedings of International Design and Technology of IntegratedSystems in Nanoscale Era, Sep. 2007, pp. 164?169.
  • R. A. Rohrer, Circuit partitioning simplified, IEEE Transactions on Circuitsand Systems, vol. 35, no. 1, pp. 2?5, Jan. 1988.
  • Predictive technology model, 2011, available:http://ptm.asu.edu/.
  • Placement of iscas89 benchmark circuits, 1989,available:http://www.ece.wisc.edu/vlsi/tools/iscas-placement/index.html.
  • P. Restle, D. Shan, D. Hogenmiller, Y. Kim, A. Drake, J. Hibbeler, T. Bucelot,G. Still, K. Jenkins, and J. Friedrich, Wide-frequency-range resonant clock withon-the-fly mode changing for the powertm microprocessor, in Proceedings ofIEEE International Solid-State Circuits Conference Digest of Technical Papers,Feb. 2014, pp. 100?101.
  • P. E. Gronowski, W. J. Bowhill, R. P. Preston, M. K. Gowan, and R. L. Allmon, High-performance microprocessor, vol. 33, no. 5, pp. 676?686, May 1998.
  • P. Chakrabarti, V. Bhatt, D. Hill, and A. Cao, Clock mesh framework, in Pro-ceedings of the IEEE International Symposium on Quality Electronic Design,Mar. 2012, pp. 381?386.
  • N. Z. Haron and S. Hamdioui, Why is cmos scaling coming to and end? in Pro-ceedings of the 3rd International Design and Test Workshop (IDT), Dec. 2008,pp. 98?103.
  • M. R. Guthaus, X. Hu, G.Wilke, G. Flach, and R. Reis, High-performance clockmesh optimization, ACM Transactions on Design Automation of Electronic Sys-tems, vol. 17, no. 3, pp. 33:1?33:17, Jun. 2012.
  • M. P. Desai, R. Cvijetic, and J. Jensen, Sizing of clock distribution networksfor high performance cpu chips, in Proceedings of the 33th ACM/IEEE DesignAutomation Conference, 1996, pp. 389?394.
  • M. Edahiro, A clustering-based optimization algorithm in zero-skew routings, in Proceedings of the 30th ACM/IEEEDesign Automation Conference, Jun. 1993,pp. 612?616.
  • M. Donno, A. Ivaldi, L. Benini, and E. Macii, Clock-tree power optimizationbased on rtl clock-gating, in Proceedings of the ACM/IEEE Design AutomationConference, Jun. 2003, pp. 622?627.78
  • M. Cho, D. Z. Pan, and R. Puri, Novel binary linear programming for high performanceclock mesh synthesis, in Proceedings of the ACM/IEEE InternationalConference on Computer-Aided Design, Nov. 2010, pp. 438?443.81
  • M. Celik, L. Pileggi, and A. Odabasioglu, IC Interconnect Analysis. Springer,2002.
  • M. Alioto, G. Palumbo, and M. Pennisi, Understanding the effect of processvariations on the delay of static and domino logic, IEEE Transactions on VeryLarge Scale Integration (VLSI) Systems, vol. 18, no. 5, pp. 697?710, May 2010.
  • M. A. B. Jackson, A. Srinnivasan, and E. S. Kuh, Clock routing for highperformanceics, in Proceedings of the 27th ACM/IEEE Design AutomationConference, Jun. 1990, pp. 573?579.
  • J.-S. Yang, A. Rajaram, N. Shi, J. Chen, and D. Z. Pan, Sensitivity based linkinsertion for variation tolerant clock network synthesis, in Proceedings of the8th International Symposium on Quality Electronic Design, Mar. 2007, pp. 398?403.
  • J. Yang, X. Zhou, M. Chrobak, Y. Zhang, and L. Jin, Dynamic thermal managementthrough task scheduling, in Proceedings of IEEE International Symposiumon Performance Analysis of System and Software, Apr. 2008, pp. 191?201.77
  • J. R. Lorch and A. J. Smith, Reducing processor power consumption by improvingprocessor time management in a single-user operating system, in Pro-ceedings of the Second ACMInternational Conference on Mobile Computing andNetworking, Nov. 1996, pp. 143?154.
  • J. R. Black, Electromigration ? a brief survey and some recent results, IEEETrans. on Electron Devices, vol. ED-16, no. 4, pp. 338?347, Apr. 1969.
  • J. Lu, X. Mao, and B. Taskin, Integrated clock mesh synthesis with incrementalregister placement, IEEE Transactions on Computer-Aided Design of IntegratedCircuits and Systems, vol. 31, no. 2, pp. 217?227, Feb. 2012.
  • J. G. Xi and W. W.-M. Dai, Useful-skew clock routing with gate sizing for lowpower design, Journal of VLSI Signal Processing for Signal, Image and VideoTechnology, vol. 16, no. 2-3, pp. 163?179, Jun. 1997.
  • J. G. Xi and W. W.-M. Dai, Buffer insertion and sizing under process variationfor low power clock distribution, in Proceedings of the ACM/IEEE Design Au-tomation Conference, Jun. 1995, pp. 491?496.
  • J. Cong, A. B. Kahng, C.-K. Koh, and C.-W. A. Tsao, Bounded-skew clock andsteiner routing, ACM Transactions on Design Automation of Electronic Systems,vol. 3, no. 3, pp. 341?388, Jul. 1998.
  • ISPD, ISPD 2010 clock network synthesis contest, 2010, available:http://archive.sigda.org/ispd/contests/10/ispd10cns.html.76
  • H. Chen and et al., A sliding window scheme for accurate clock mesh analysis, in Proceedings of the ACM/IEEE International Conference on Computer-AidedDesign, Nov. 2005, pp. 939?946.
  • H. Chang and S. S. Sapatnekar, Statistical timing analysis under spatial correlations, IEEE Transactions on Computer-Aided Design of Integrated Circuits andSystems, vol. 24, no. 9, pp. 1467?1482, Sep. 2005.
  • G. Venkataraman, J. H. Z. Feng, and P. Li, Combinatorial algorithms for fastclock mesh optimization, IEEE Transactions on Very Large Scale Integration(VLSI) Systems, vol. 18, no. 1, pp. 131?141, Jan. 2010.
  • G. E. Tellez and M. Sarrafzadeh, Minimal buffer insertion in clock trees withskew and slew rate constraints, IEEE Transactions on Computer-Aided Designof Integrated Circuits and Systems, vol. 16, no. 4, pp. 333?342, Apr. 1997.
  • E. Malavasi, S. Zanella, and M. Cao, Impact analysis of process variability onclock skew, in Proceedings of the 3th International Symposium on Quality Elec-tronic Design, Mar. 2002, pp. 129?132.
  • D. Panigrahi, C. Chiasserini, S. Dey, and R. Rao, Battery life estimation of mobileembedded system, in Proceedings of 4th International Conference on VLSIDesign, Jan. 2001, pp. 57?63.
  • C.-W. A. Tsao and C.-K. Koh, Ust/dme: A clock tree router for general skewconstraints, ACM Transactions on Design Automation of Electronic Systems,vol. 7, no. 3, pp. 359?379, Jul. 2002.
  • B. W. Kernighan and S. Lin, An efficient heuristic procedure for partitioninggraphs, The Bell System Technical Journal, vol. 49, no. 1, pp. 291?307, 1970.
  • A. Vittal and M. M.-Sadowska, Power optimal buffered clock tree design, inProceedings of the ACM/IEEE Design Automation Conference, Jun. 1995, pp.497?502.
  • A. Rajaram, J. Hu, and R. Mahapatra, Reducing clock skew variability viacrosslinks, IEEE Transactions on Computer-Aided Design of Integrated Circuitsand Systems, vol. 25, no. 6, pp. 1176?1182, Jun. 2006.
  • A. Rajaram and D. Z. Pan, Meshworks: a comprehensive framework for optimizedclock mesh network synthesis, IEEE Transactions on Computer-AidedDesign of Integrated Circuits and Systems, vol. 29, no. 12, pp. 1945?1958, Dec.2010.
  • A. B. Kahng and C.-W.A. Tsao, Practical bounded-skew clock routing, Journalof VLSI Signal Processing for Signal, Image and Video Technology, vol. 16, no.2-3, pp. 199?215, Jun. 1997.
  • A. Agarwal, D. Blaauw, and V. Zolotov, Statistical clock skew analysis consideringintra-die process variations, in Proceedings of the ACM/IEEE Interna-tional Conference on Computer-Aided Design, Nov. 2003, pp. 914?921.